Department of Low-Level Affairs
Sakshat Sachdeva · IIIT Delhi
Okhla Phase III, New Delhi 110020
Lab: four live exhibits, running in your browser right now
Nothing here is a video. Each exhibit is a small simulation written in plain JavaScript, seeded fresh on every load. Numbers you see are being computed as you read.
Currently: GRM Intern at IBM Research, causal inference with time-series foundation models. President of the Placement Committee and the Quant Society at IIIT Delhi. BTech CS, class of 2027.
Prev: GEP Worldwide, Scrite.io, NX Block Trades, Banavo.ai, ProCohat. Co-author of a paper under review at ICLR 2027. Open to 2027 systems and quant roles.
Schedule
EventDate
Gigtern, CTO & COONov 2023 – May 2025
Barkedo, Founder's OfficeNov 2023 – May 2025
ProCohat, DevOps InternJun – Aug 2024
Tale of Humankind, Program HeadJun – Dec 2024
Shipd, Problem SolverMar – May 2025
Banavo.ai, SWE InternMay – Jul 2025
NX Block Trades, Quant Research ApprenticeAug 2025 – Jan 2026
Scrite.io, Open Source Dev InternJan – May 2026
GEP Worldwide, SWE Intern (Agentic AI)May – Jul 2026
IBM Research, GRM InternJan 2026 – Present
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Exhibit A: Limit Order Book
Lock-free SPSC queue → matching engine → L2 bookSimulated flow
Msgs processed: 0Msgs/sec: 0
Engine

    
Last: —Spread: —Imbalance: —

    
 

    
Tick-to-book latency, RDTSC, last 2,000 msgs

    

    
Bar: log scale. Target from HFT-Core: P50 under 120 ns on a cold laptop core. Spikes are injected cache misses.

    
A add  C cancel  M market  T trade  — same op codes as the real engine's message enum.

    
 

    
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Exhibit B: Game Boy CPU Trace

    
SM83 core, 4.19 MHz, 160×144 framebuffer, trace sampled 1 in 48Simulated execution

    
Frame: 0LY: 0Cycles: 0

    
Core

    

      
      

    

    
AF 0000  BC 0000  DE 0000  HL 0000  SP FFFEIME 1

    
Pocket Pixel runs the real thing: C++ core, JNI bridge, 100+ titles at 60 FPS, 5,000+ installs. This is a toy trace with a scrolling tile map and one sprite, so the page stays light.

    
 

    
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Exhibit C: Causal Estimator Converging

    
Panel of units, treatment at t=30, Difference-in-DifferencesSimulated data

    
Units: 0Truth τ: +2.00DiD τ̂: —SE: —

    
Sampler

    

      
Treated vs control, group means

      
KL certificate vs estimator bias, 11 representations

    

    
Estimate path, last 40 drawscorr —

    

    
The IBM work: a KL-divergence certificate on the learned representation predicts how biased a downstream treatment-effect estimator will be (corr 0.976 across 11 representations). Now extending to causal task arithmetic over merged fine-tunes.

    
 

    
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Exhibit D: Career Wire Log

    
Two parties on one wire: life deals, Sakshat repliesReal events, fake timestamps

    
Trace

    
Msg: 000Stack: 0 XP

    
Δt
Life sends
Sakshat replies, with think time

    
A accept  W win  F fold  R raise  S ship  P publish. Think time is how long he pretended to deliberate.

    
 

    
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Colophon

    
One HTML file, no framework, no build step, about 30 KB. Hosted on GitHub Pages. Style borrowed with admiration from the Sequoia pokerbot tournament page.

    
Everything above is simulated on your machine. The order book, the CPU, the panel data and the wire log restart when you reload.

    
 

    
← Back to the normal website  Source

    
© Sakshat Sachdeva · 2026